Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller

International audienceTo deal with Wireless Sensor Node's energy constraints , new architectural solutions have to be found. This paper proposes to analyze a WSN microcontroller subsystem power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller. This block is able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node's sub-modules. Power simulations of a microcontroller subsystem based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. Results are presented for applicative scenarios ranging from very low to high activity rates. This study exhibits power gains from 14.5% to 76% in the full range attesting the future design of this new module

Power Gain Estimation of an Event-driven Wake-Up Controller dedicated to WSN's Microcontroller

Abstract-To deal with Wireless Sensor Node's energy constraints, new architectural solutions have to be found. This paper proposes to analyze a WSN microcontroller sub-system power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller. This block is able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node's sub-modules. Power simulations of a microcontroller sub-system based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. Results are presented for applicative scenarios ranging from very low to high activity rates. This study exhibits power gains from 14.5% to 76% in the full range attesting the future design of this new module

Aging, memory and rejuvenation: some lessons from simple models

Many recent experiments probed the off equilibrium dynamics of spin glasses and other glassy systems through temperature cycling protocols and observed memory and rejuvenation phenomena. Here we show through numerical simulations, using powerful algorithms, that such features can already be observed to some extent in simple models such as two dimensional ferromagnets. We critically discuss these results and review some aspects of the literature in the light of our findings.Comment: 10 pages, 8 figures. Contribution to the Proceedings of the Summerschool "Ageing and the glass transition", Luxembourg 14-25 Sept. 200

Conception d'un processeur ultra basse consommation pour les noeuds de capteurs sans fil

This PhD work focuses on the reduction of energy consumption and wake up time reduction of a WSN node microcontroller through innovations at architectural, circuit and power management level. This work proposes a partitioned microcontroller architecture between a programmable wake up processor, named Wake Up Controller on which this work is focused, and a main processor. The first deals with the common tasks of a wireless sensor node while the second manages the irregular tasks. TheWake Up Controller proposed in this work is a 16-bit RISC processor whose instruction set has been adapted to handle regular tasks of a sensor node. It only executes code on interruptions. It is implemented in asynchronous / synchronous mixed logic to improve wake up time and energy. A circuit was fabricated in a 28nm UTBB FDSOI technology integrating the Wake Up Controller. The core reaches 11,9 MIPS for 125 μW average power consumption in active phase and wakes up from sleep mode in 55ns from eight possible interruption sources. The static power consumption is around 4μW for the asynchronous logic core at 0.6V without power gating and 500nW when gated.Les travaux de cette thèse se concentrent sur la réduction de l'énergie consommée et l'amélioration des temps de réveil du microcontrôleur par des innovations au niveau de l'architecture, du circuit et de la gestion de l'énergie. Ces travaux proposent une architecture de microcontrôleur partitionnée entre un processeur de réveil programmable, appelé Wake Up Controller, s'occupant des tâches courantes du nœud de capteurs et un processeur principal gérant les tâches irrégulières. Le Wake Up Controller proposé dans ces travaux de thèse est un processeur RISC 16-bit dont le jeu d'instructions a été adapté pour gérer les tâches régulières du nœud, et n'exécute que du code sur interruptions. Il est implémenté en logique mixte asynchrone/synchrone. Un circuit a été fabriqué en technologie UTBB FDSOI 28nm intégrant le Wake-Up Controller. Le cœur atteint une performance de 11,9 MIPS pour 125μW de consommation moyenne en phase active et un réveil depuis le mode de veille en 55ns pour huit sources de réveil possibles. La consommation statique est d'environ 4μW pour le cœur logique asynchrone à 0,6V sans utilisation de gestion d'alimentation (power gating) et d'environ 500nW avec

Design of an ultra low power processor for wireless sensor nodes

Les travaux de cette thèse se concentrent sur la réduction de l'énergie consommée et l'amélioration des temps de réveil du microcontrôleur par des innovations au niveau de l'architecture, du circuit et de la gestion de l'énergie. Ces travaux proposent une architecture de microcontrôleur partitionnée entre un processeur de réveil programmable, appelé Wake Up Controller, s'occupant des tâches courantes du nœud de capteurs et un processeur principal gérant les tâches irrégulières. Le Wake Up Controller proposé dans ces travaux de thèse est un processeur RISC 16-bit dont le jeu d'instructions a été adapté pour gérer les tâches régulières du nœud, et n'exécute que du code sur interruptions. Il est implémenté en logique mixte asynchrone/synchrone. Un circuit a été fabriqué en technologie UTBB FDSOI 28nm intégrant le Wake-Up Controller. Le cœur atteint une performance de 11,9 MIPS pour 125μW de consommation moyenne en phase active et un réveil depuis le mode de veille en 55ns pour huit sources de réveil possibles. La consommation statique est d'environ 4μW pour le cœur logique asynchrone à 0,6V sans utilisation de gestion d'alimentation (power gating) et d'environ 500nW avec.This PhD work focuses on the reduction of energy consumption and wake up time reduction of a WSN node microcontroller through innovations at architectural, circuit and power management level. This work proposes a partitioned microcontroller architecture between a programmable wake up processor, named Wake Up Controller on which this work is focused, and a main processor. The first deals with the common tasks of a wireless sensor node while the second manages the irregular tasks. TheWake Up Controller proposed in this work is a 16-bit RISC processor whose instruction set has been adapted to handle regular tasks of a sensor node. It only executes code on interruptions. It is implemented in asynchronous / synchronous mixed logic to improve wake up time and energy. A circuit was fabricated in a 28nm UTBB FDSOI technology integrating the Wake Up Controller. The core reaches 11,9 MIPS for 125 μW average power consumption in active phase and wakes up from sleep mode in 55ns from eight possible interruption sources. The static power consumption is around 4μW for the asynchronous logic core at 0.6V without power gating and 500nW when gated

Conception d'un processeur ultra basse consommation pour les noeuds de capteurs sans fil

This PhD work focuses on the reduction of energy consumption and wake up time reduction of a WSN node microcontroller through innovations at architectural, circuit and power management level. This work proposes a partitioned microcontroller architecture between a programmable wake up processor, named Wake Up Controller on which this work is focused, and a main processor. The first deals with the common tasks of a wireless sensor node while the second manages the irregular tasks. TheWake Up Controller proposed in this work is a 16-bit RISC processor whose instruction set has been adapted to handle regular tasks of a sensor node. It only executes code on interruptions. It is implemented in asynchronous / synchronous mixed logic to improve wake up time and energy. A circuit was fabricated in a 28nm UTBB FDSOI technology integrating the Wake Up Controller. The core reaches 11,9 MIPS for 125 μW average power consumption in active phase and wakes up from sleep mode in 55ns from eight possible interruption sources. The static power consumption is around 4μW for the asynchronous logic core at 0.6V without power gating and 500nW when gated.Les travaux de cette thèse se concentrent sur la réduction de l'énergie consommée et l'amélioration des temps de réveil du microcontrôleur par des innovations au niveau de l'architecture, du circuit et de la gestion de l'énergie. Ces travaux proposent une architecture de microcontrôleur partitionnée entre un processeur de réveil programmable, appelé Wake Up Controller, s'occupant des tâches courantes du nœud de capteurs et un processeur principal gérant les tâches irrégulières. Le Wake Up Controller proposé dans ces travaux de thèse est un processeur RISC 16-bit dont le jeu d'instructions a été adapté pour gérer les tâches régulières du nœud, et n'exécute que du code sur interruptions. Il est implémenté en logique mixte asynchrone/synchrone. Un circuit a été fabriqué en technologie UTBB FDSOI 28nm intégrant le Wake-Up Controller. Le cœur atteint une performance de 11,9 MIPS pour 125μW de consommation moyenne en phase active et un réveil depuis le mode de veille en 55ns pour huit sources de réveil possibles. La consommation statique est d'environ 4μW pour le cœur logique asynchrone à 0,6V sans utilisation de gestion d'alimentation (power gating) et d'environ 500nW avec

Asynchronous Wake Up Controller for WSN’s Microcontroller: Power Simulation and Specifications

International audienc

Time series visualization tools through a Virtual Observatory in geodesy

International audienceThis poster presents the context of the astronomical Virtual Observatory (VO), an ambitious international proposal to provide uniform, convenient access to disparate, geographically dispersed archives of astronomical data from software which runs on the computer on the astronomer's desktop. The VO could be of interest for the geodetic community: we present here some of our efforts in this direction that we have recently achieved, concerning the visualization of time series obtained from the analysis of space geodetic techniques. Some of these products are now natively built and archived following the data format recommended by IVOA, the VO-Table format. We present this format, which is based on the XML format, and we list the reasons why we chose to use it. Astronomers using that Virtual Observatory are now organized within an international association called the International Virtual Observatory Alliance (IVOA). As noted on the IVOA website (http://www.ivoa.net/), IVOA was formed in June 2002 with a mission to "facilitate the international coordination and collaboration necessary for the development and deployment of the tools, systems and organizational structures necessary to enable the international utilization of astronomical archives as an integrated and interoperating virtual observatory